410 lines
10 KiB
NASM
410 lines
10 KiB
NASM
;{ ****************************************************************************** }
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;{ * https://zpascal.net * }
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;{ * https://github.com/PassByYou888/zAI * }
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;{ * https://github.com/PassByYou888/ZServer4D * }
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;{ * https://github.com/PassByYou888/PascalString * }
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;{ * https://github.com/PassByYou888/zRasterization * }
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;{ * https://github.com/PassByYou888/CoreCipher * }
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;{ * https://github.com/PassByYou888/zSound * }
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;{ * https://github.com/PassByYou888/zChinese * }
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;{ * https://github.com/PassByYou888/zExpression * }
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;{ * https://github.com/PassByYou888/zGameWare * }
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;{ * https://github.com/PassByYou888/zAnalysis * }
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;{ * https://github.com/PassByYou888/FFMPEG-Header * }
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;{ * https://github.com/PassByYou888/zTranslate * }
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;{ * https://github.com/PassByYou888/InfiniteIoT * }
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;{ * https://github.com/PassByYou888/FastMD5 * }
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;{ ****************************************************************************** }
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; MD5_Transform-x64
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; MD5 transform routine oprimized for x64 processors
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; Copyright 2018 Ritlabs, SRL
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; The 64-bit version is written by Maxim Masiutin <max@ritlabs.com>
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; The main advantage of this 64-bit version is that
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; it loads 64 bytes of hashed message into 8 64-bit registers
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; (RBP, R8, R9, R10, R11, R12, R13, R14) at the beginning,
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; to avoid excessive memory load operations
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; througout the routine.
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; To operate with 32-bit values store in higher bits
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; of a 64-bit register (bits 32-63) uses "Ror" by 32;
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; 8 macro variables (M1-M8) are used to keep record
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; or corrent state of whether the register has been
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; Ror'ed or not.
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; It also has an ability to use Lea instruction instead
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; of two sequental Adds (uncomment UseLea=1), but it is
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; slower on Skylake processors. Also, Intel in the
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; Optimization Reference Maual discourages us of
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; Lea as a replacement of two adds, since it is slower
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; on the Atom processors.
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; MD5_Transform-x64 is released under a dual license,
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; and you may choose to use it under either the
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; Mozilla Public License 2.0 (MPL 2.1, available from
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; https://www.mozilla.org/en-US/MPL/2.0/) or the
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; GNU Lesser General Public License Version 3,
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; dated 29 June 2007 (LGPL 3, available from
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; https://www.gnu.org/licenses/lgpl.html).
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; MD5_Transform-x64 is based
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; on the following code by Peter Sawatzki.
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; The original notice by Peter Sawatzki follows.
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; ==============================================================
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;
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; MD5_386.Asm - 386 optimized helper routine for calculating
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; MD Message-Digest values
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; written 2/2/94 by
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;
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; Peter Sawatzki
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; Buchenhof 3
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; D58091 Hagen, Germany Fed Rep
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;
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; EMail: Peter@Sawatzki.de
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; EMail: 100031.3002@compuserve.com
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; WWW: http://www.sawatzki.de
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;
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;
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; original C Source was found in Dr. Dobbs Journal Sep 91
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; MD5 algorithm from RSA Data Security, Inc.
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.CODE
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; You can compile this code using Microsoft Macro Assembler
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; ml64.exe /c md5_64.asm
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; Uncomment the line below if you wish to have
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; a "Lea" instruction instead of two subsequent "Add".
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; UseLea=1
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; The AA macro adds r to ac to a and stores result to r
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; r and a can be either 32-bit (for the "Add" version)
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; or 64-bit (for the "Lea" version)
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AA Macro r32,r64,ac,a32,a64
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IFDEF UseLea
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Lea r64, [r64+ac+a64]
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ELSE
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Add r32, ac
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Add r32, a32
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ENDIF
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EndM
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; The JJ macro adds value from state buffer to the "a" register
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; The "a" register can be either 32-bit (for the "Add" version)
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; or 64-bit (for "Lea") - in this case it is passed as "r"
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JJ Macro a,x,ac,r
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IFE x
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IF M1
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Ror RBp, 32
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M1=0
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ENDIF
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AA a, r, ac, EBp, RBp
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ENDIF
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IFE x-1
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IFE M1
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Ror RBp, 32
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M1=1
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ENDIF
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AA a, r, ac, EBp, RBp
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ENDIF
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IFE x-2
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IF M2
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Ror R8, 32
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M2=0
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ENDIF
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AA a, r, ac, R8d, R8
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ENDIF
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IFE x-3
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IFE M2
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Ror R8, 32
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M2=1
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ENDIF
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AA a, r, ac, R8d, R8
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ENDIF
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IFE x-4
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IF M3
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Ror R9, 32
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M3=0
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ENDIF
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AA a, r, ac, R9d, R9
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ENDIF
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IFE x-5
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IFE M3
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Ror R9, 32
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M3=1
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ENDIF
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AA a, r, ac, R9d, R9
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ENDIF
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IFE x-6
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IF M4
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Ror R10, 32
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M4=0
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ENDIF
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AA a, r, ac, R10d, R10
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ENDIF
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IFE x-7
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IFE M4
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Ror R10, 32
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M4=1
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ENDIF
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AA a, r, ac, R10d, R10
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ENDIF
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IFE x-8
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IF M5
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Ror R11, 32
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M5=0
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ENDIF
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AA a, r, ac, R11d, R11
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ENDIF
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IFE x-9
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IFE M5
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Ror R11, 32
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M5=1
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ENDIF
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AA a, r, ac, R11d, R11
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ENDIF
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IFE x-10
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IF M6
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Ror R12, 32
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M6=0
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ENDIF
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AA a, r, ac, R12d, R12
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ENDIF
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IFE x-11
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IFE M6
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Ror R12, 32
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M6=1
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ENDIF
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AA a, r, ac, R12d, R12
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ENDIF
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IFE x-12
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IF M7
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Ror R13, 32
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M7=0
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ENDIF
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AA a, r, ac, R13d, R13
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ENDIF
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IFE x-13
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IFE M7
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Ror R13, 32
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M7=1
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ENDIF
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AA a, r, ac, R13d, R13
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ENDIF
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IFE x-14
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IF M8
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Ror R14, 32
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M8=0
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ENDIF
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AA a, r, ac, R14d, R14
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ENDIF
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IFE x-15
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IFE M8
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Ror R14, 32
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M8=1
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ENDIF
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AA a, r, ac, R14d, R14
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ENDIF
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EndM
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FF Macro a,b,c,d,x,s,ac,r
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; a:= ROL (a+x+ac + (b And c Or Not b And d), s) + b
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JJ a, x, ac, r
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Mov ESI, b
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Not ESI
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And ESI, d
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Mov EDI, c
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And EDI, b
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Or ESI, EDI
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Add a, ESI
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Rol a, s
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Add a, b
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EndM
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GG Macro a,b,c,d,x,s,ac,r
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; a:= ROL (a+x+ac + (b And d Or c And Not d), s) + b
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JJ a, x, ac, r
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Mov ESI, d
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Not ESI
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And ESI, c
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Mov EDI, d
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And EDI, b
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Or ESI, EDI
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Add a, ESI
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Rol a, s
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Add a, b
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EndM
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HH Macro a,b,c,d,x,s,ac,r
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; a:= ROL (a+x+ac + (b Xor c Xor d), s) + b
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JJ a, x, ac, r
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Mov ESI, d
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Xor ESI, c
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Xor ESI, b
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Add a, ESI
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Rol a, s
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Add a, b
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EndM
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II Macro a,b,c,d,x,s,ac,r
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; a:= ROL (a+x+ac + (c Xor (b Or Not d)), s) + b
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JJ a, x, ac, r
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Mov ESI, d
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Not ESI
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Or ESI, b
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Xor ESI, c
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Add a, ESI
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Rol a, s
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Add a, b
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EndM
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MD5_Transform Proc
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Public MD5_Transform
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; save registers that the caller requires to be restored
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Push RBx
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Push RSi
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Push RDi
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Push RBp
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Push R12
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Push R13
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Push R14
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; First parameter is passed in RCX, Second - in RDX
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; State - in RCX
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; Message - in RDX
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M1 = 0
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M2 = 0
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M3 = 0
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M4 = 0
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M5 = 0
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M6 = 0
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M7 = 0
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M8 = 0
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Mov R14, RDX ; Now the message buffer offset is in R14
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Mov RSi, Rcx ; Now state structure offset is in RSi
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Push Rsi ; State -> Stack
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Mov EAx, [RSi]
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Mov EBx, [RSi+4]
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Mov ECx, [RSi+8]
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Mov EDx, [RSi+12]
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Mov RBP, [R14+4*0]
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FF EAx,EBx,ECx,EDx, 0, 7, 0d76aa478h, RAx ; 1
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FF EDx,EAx,EBx,ECx, 1, 12, 0e8c7b756h, RDx ; 2
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Mov R8, [R14+4*2]
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FF ECx,EDx,EAx,EBx, 2, 17, 0242070dbh, RCx ; 3
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FF EBx,ECx,EDx,EAx, 3, 22, 0c1bdceeeh, RBx ; 4
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Mov R9, [R14+4*4]
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FF EAx,EBx,ECx,EDx, 4, 7, 0f57c0fafh, RAx ; 5
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FF EDx,EAx,EBx,ECx, 5, 12, 04787c62ah, RDx ; 6
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Mov R10, [R14+4*6]
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FF ECx,EDx,EAx,EBx, 6, 17, 0a8304613h, RCx ; 7
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FF EBx,ECx,EDx,EAx, 7, 22, 0fd469501h, RBx ; 8
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Mov R11, [R14+4*8]
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FF EAx,EBx,ECx,EDx, 8, 7, 0698098d8h, RAx ; 9
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FF EDx,EAx,EBx,ECx, 9, 12, 08b44f7afh, RDx ; 10
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Mov R12, [R14+4*10]
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FF ECx,EDx,EAx,EBx, 10, 17, 0ffff5bb1h, RCx ; 11
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FF EBx,ECx,EDx,EAx, 11, 22, 0895cd7beh, RBx ; 12
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Mov R13, [R14+4*12]
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FF EAx,EBx,ECx,EDx, 12, 7, 06b901122h, RAx ; 13
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FF EDx,EAx,EBx,ECx, 13, 12, 0fd987193h, RDx ; 14
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Mov R14, [R14+4*14]
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FF ECx,EDx,EAx,EBx, 14, 17, 0a679438eh, RCx ; 15
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FF EBx,ECx,EDx,EAx, 15, 22, 049b40821h, RBx ; 16
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GG EAx,EBx,ECx,EDx, 1, 5, 0f61e2562h, RAx ; 17
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GG EDx,EAx,EBx,ECx, 6, 9, 0c040b340h, RDx ; 18
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GG ECx,EDx,EAx,EBx, 11, 14, 0265e5a51h, RCx ; 19
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GG EBx,ECx,EDx,EAx, 0, 20, 0e9b6c7aah, RBx ; 20
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GG EAx,EBx,ECx,EDx, 5, 5, 0d62f105dh, RAx ; 21
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GG EDx,EAx,EBx,ECx, 10, 9, 002441453h, RDx ; 22
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GG ECx,EDx,EAx,EBx, 15, 14, 0d8a1e681h, RCx ; 23
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GG EBx,ECx,EDx,EAx, 4, 20, 0e7d3fbc8h, RBx ; 24
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GG EAx,EBx,ECx,EDx, 9, 5, 021e1cde6h, RAx ; 25
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GG EDx,EAx,EBx,ECx, 14, 9, 0c33707d6h, RDx ; 26
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GG ECx,EDx,EAx,EBx, 3, 14, 0f4d50d87h, RCx ; 27
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GG EBx,ECx,EDx,EAx, 8, 20, 0455a14edh, RBx ; 28
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GG EAx,EBx,ECx,EDx, 13, 5, 0a9e3e905h, RAx ; 29
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GG EDx,EAx,EBx,ECx, 2, 9, 0fcefa3f8h, RDx ; 30
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GG ECx,EDx,EAx,EBx, 7, 14, 0676f02d9h, RCx ; 31
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GG EBx,ECx,EDx,EAx, 12, 20, 08d2a4c8ah, RBx ; 32
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HH EAx,EBx,ECx,EDx, 5, 4, 0fffa3942h, RAx ; 33
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HH EDx,EAx,EBx,ECx, 8, 11, 08771f681h, RDx ; 34
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HH ECx,EDx,EAx,EBx, 11, 16, 06d9d6122h, RCx ; 35
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HH EBx,ECx,EDx,EAx, 14, 23, 0fde5380ch, RBx ; 36
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HH EAx,EBx,ECx,EDx, 1, 4, 0a4beea44h, RAx ; 37
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HH EDx,EAx,EBx,ECx, 4, 11, 04bdecfa9h, RDx ; 38
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HH ECx,EDx,EAx,EBx, 7, 16, 0f6bb4b60h, RCx ; 39
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HH EBx,ECx,EDx,EAx, 10, 23, 0bebfbc70h, RBx ; 40
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HH EAx,EBx,ECx,EDx, 13, 4, 0289b7ec6h, RAx ; 41
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HH EDx,EAx,EBx,ECx, 0, 11, 0eaa127fah, RDx ; 42
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HH ECx,EDx,EAx,EBx, 3, 16, 0d4ef3085h, RCx ; 43
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HH EBx,ECx,EDx,EAx, 6, 23, 004881d05h, RBx ; 44
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HH EAx,EBx,ECx,EDx, 9, 4, 0d9d4d039h, RAx ; 45
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HH EDx,EAx,EBx,ECx, 12, 11, 0e6db99e5h, RDx ; 46
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HH ECx,EDx,EAx,EBx, 15, 16, 01fa27cf8h, RCx ; 47
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HH EBx,ECx,EDx,EAx, 2, 23, 0c4ac5665h, RBx ; 48
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II EAx,EBx,ECx,EDx, 0, 6, 0f4292244h, RAx ; 49
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II EDx,EAx,EBx,ECx, 7, 10, 0432aff97h, RDx ; 50
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II ECx,EDx,EAx,EBx, 14, 15, 0ab9423a7h, RCx ; 51
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II EBx,ECx,EDx,EAx, 5, 21, 0fc93a039h, RBx ; 52
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II EAx,EBx,ECx,EDx, 12, 6, 0655b59c3h, RAx ; 53
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II EDx,EAx,EBx,ECx, 3, 10, 08f0ccc92h, RDx ; 54
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II ECx,EDx,EAx,EBx, 10, 15, 0ffeff47dh, RCx ; 55
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II EBx,ECx,EDx,EAx, 1, 21, 085845dd1h, RBx ; 56
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II EAx,EBx,ECx,EDx, 8, 6, 06fa87e4fh, RAx ; 57
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II EDx,EAx,EBx,ECx, 15, 10, 0fe2ce6e0h, RDx ; 58
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II ECx,EDx,EAx,EBx, 6, 15, 0a3014314h, RCx ; 59
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II EBx,ECx,EDx,EAx, 13, 21, 04e0811a1h, RBx ; 60
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II EAx,EBx,ECx,EDx, 4, 6, 0f7537e82h, RAx ; 61
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II EDx,EAx,EBx,ECx, 11, 10, 0bd3af235h, RDx ; 62
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II ECx,EDx,EAx,EBx, 2, 15, 02ad7d2bbh, RCx ; 63
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II EBx,ECx,EDx,EAx, 9, 21, 0eb86d391h, RBx ; 64
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Pop RSi ; get State pointer from stack
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Add [RSi], EAx
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Add [RSi+4], EBx
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Add [RSi+8], ECx
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Add [RSi+12], EDx
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; restore volatile registers
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Pop R14
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Pop R13
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Pop R12
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Pop RBp
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Pop RDi
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Pop RSi
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Pop RBx
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Ret
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MD5_Transform EndP
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End
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; That's All Folks!
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